3d7522 monolithic manchester decoder (series 3d7522) d a ta delay devices, i n c. ? 3 features packages 8 7 6 5 1 2 3 4 rx cl k n/c gnd vdd n/c n/c dat b 3d 7522z- xxx s o i c ( . 150) 14 13 12 11 10 9 8 1 2 3 4 5 6 7 rx n/c n/c cl k n/c n/c gnd vdd n/c n/c n/c n/c n/c dat b 3d 7522d - xxx s o i c ( . 1 5 0 ) ? all-silicon, low-power cmos technology ? ttl/cmos compatible inputs and outputs ? vapor phase, ir and wave solderable ? low ground bounce noise ? maximum dat a rat e : 50 mbaud ? data rate range: 15% ? lock-in time: 1 bit f o r mechanical dimensions, click here . f o r package marking details, click here . functional description the 3d7522 product family consists of monolithic cmos manchester decoders. the unit accepts at the rx input a bi-phase-level, embedded-clock signal. in this encoding mode, a logic one is represented by a high-to-low transition within the bit cell, while a logic zero is represented by a low-to-high transition. the recovered clock and data signals are presented on clk and datb, respectively, with the data signal inverted. the operating baud rate (in mbaud) is specified by the dash number. the input baud rate may vary by as much as 15% from the nominal device baud rate without compromising the integrity of the information received. because the 3d7522 is not pll-based, it does not r equire a long preamble in order to lock onto the received signal. rather, the device requires at most one bit cell before the data pr esented at the output is valid. this is extremely useful in cases where the information arrives in bursts and the input is otherwise turned off. the all-cmos 3d7522 integrated circuit has been designed as a reliable, economic alternative to hybrid ttl manchester decoders. it is ttl- and cmos-compatib le, capable of driving ten 74ls-type loads. it is offered in space saving surface mount 8-pin and 14-pin soics. table 1: part number specifications pin descriptions rx signal input clk signal output (clock) datb signal output (data) vdd +5 volts gnd ground pa rt ba ud ra te (mbaud) n u m b e r n o m i n a l mi n i m u m m a x i m u m 3 d 7 5 2 2 - 0 . 5 0 . 5 0 0 . 4 3 0 . 5 7 3 d 7 5 2 2 - 1 1 . 0 0 0 . 8 5 1 . 1 5 3 d 7 5 2 2 - 5 5 . 0 0 4 . 2 5 5 . 7 5 3 d 7 5 2 2 - 1 0 1 0 . 0 0 8 . 5 0 1 1 . 5 0 3 d 7 5 2 2 - 2 0 2 0 . 0 0 1 7 . 0 0 2 3 . 0 0 3 d 7 5 2 2 - 2 5 2 5 . 0 0 2 1 . 2 5 2 8 . 7 5 3 d 7 5 2 2 - 5 0 5 0 . 0 0 4 2 . 5 0 5 7 . 5 0 notes: a n y baud rate betw een 0.5 and 50 mbaud not show n is also av ailable at no extra cost. ? 2007 data delay dev i ces doc #06002 data delay devices, inc. 1 10/31/2007 3 mt. prospect ave. clifton, nj 07013
3d7522 application notes the 3d7522 manchester decoder samples the input at precise pre-selected intervals to retrieve the data and to recover the clock from the received data stream. its architecture comprises finely tuned delay elements and proprietary circuitry which, in conjunc tion with other circuits, implement the data decoding and clock recovery function. output signal characteristics the 3d7522 presents at its outputs the decoded data (inverted) and the recovered clock. the decoded data is v a lid at the rising edge of the clock. the clock recovery function operates in two modes dictated by the input data stream bit sequence. when a data bit is succeeded by its inverse, the clock recovery circuit is engaged and forces the clock output low for a time equal to one ov er tw ice the baud rate . otherwis e , the input is presented at the clock output unchanged, s h ifted in time. input signal characteristics encoded data transmitted from a source arrives at its destination corrupt ed. such corruption of the received data manifests itself as jitter and/or pulse width distortion at t he input to the device. the instantaneous deviations from nominal baud rate and/or pulse width (high or low) adversely impact the data extraction and clock recovery function if their published limits are exceeded. see table 4, allow e d baud rate/duty cy cle. when engaged, the clock recovery circuit generates a low-going pulse of fixed width. therefore, the clock duty cycle is strongly dependent on the baud rate, as this will affect the clock-high duration. the 3d7522 manchester decoder data input is ttl compatible. the user should assure that the 1.5 volt ttl threshold is used when referring to all timing, especially the input pulse widths. the clock output falling edge is not operated on by the c l oc k rec o very c i rc uitry. it, therefore, preserves more accurately the clock frequency information embedded in the transmitted data. therefore, it can be used, if it is desired, to retrieve clock frequency information. frequency (jitter) errors the 3d7522 manchester decoder, being a self- timed device, is tolerant of frequency modulation (jitter) present in the input data stream, provided that the input data pulse width variations remain within the allowable ranges. power supply and temperature considerations cmos integrated circuitry is strongly dependent on power supply and temperature. the monolithic 3d7522 manchester decoder utilizes novel and innovative compensation circuitry to minimize timing variations induced by fluctuations in power supply and/or temperature. . cl ock (cl k ) re ce i v e d (rx ) figur e 1 : t i m i ng d i a g r a m t c de code d 1011001 e ncode d 1011001 0 da t a (d at b) t cl t cw l t cd doc #06002 data delay devices, inc. 2 10/31/2007 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
3d7522 device specifications table 2: absolute maximum ratings p a r a m e t e r s y m b o l m i n m a x u n i t s n o t e s dc supply voltage v dd - 0 . 3 7 . 0 v input pin voltage v in - 0 . 3 v dd +0. 3 v input pin current i in - 1 0 1 0 m a 2 5 c storage temperature t st rg - 5 5 1 5 0 c lead temperature t lead 3 0 0 c 1 0 s e c table 3: dc electrical characteristics (-40c to 85c, 4.75v to 5.25v) p a r a m e t e r s y m b o l m i n m a x u n i t s n o t e s static supply current* i dd 5 m a high level input voltage v ih 2 . 0 v low level input voltage v il 0 . 8 v high level input current i ih 1 . 0 a v ih = v dd low level input current i il 1 . 0 a v il = 0v high level output current i oh - 4 . 0 m a v dd = 4.75v v oh = 2.4v low level output current i ol 4 . 0 m a v dd = 4.75v v ol = 0.4v output rise & fall time t r & t f 2 n s c ld = 5 pf *i dd (dy namic) = 2 * c ld * v dd * f input capacitance = 10 pf ty pical w here: c ld = average capacitance load/pin (pf) output load capacitance (c ld ) = 25 pf max f = input frequency (ghz) table 4: ac electrical characteristics (-40c to 85c, 4.75v to 5.25v, except as noted) parameter symbol m i n t y p m a x u n i t s n o t e s nominal input baud rate f bn 5 5 0 m b a u d allowed input baud rate deviation f b - 0 . 1 5 f bn 0 . 1 5 f bn mbaud 0c to 70c 25c, 5.00v allowed input baud rate deviation f b - 0 . 0 5 f bn 0 . 0 5 f bn mbaud 4.75v to 5.25v allowed input baud rate deviation f b - 0 . 0 3 f bn 0 . 0 3 f bn mbaud -55c to 125c 4.75v to 5.25v allowed input duty cycle 42.5 50.0 57.5 % bit cell time tc 1000/f b n s input data edge to clock falling edge t cl 0 . 7 5 t c n s clock width low t cw l 500/f bn n s 2ns or 5% clock falling edge to data transition t cd 3 . 0 4 . 0 5 . 0 n s doc #06002 data delay devices, inc. 3 10/31/2007 3 mt. prospect ave. clifton, nj 07013
3d7522 silicon delay line automated testing test conditions input: output: ambient temperature: 25 o c 3 o c r load : 10k ? 10% supply voltage (vcc): 5.0v 0.1v c load : 5pf 10% input pulse: high = 3.0v 0.1v threshold: 1.5v (rising & falling) low = 0.0v 0.1v source impedance: 50 ? max. 10k ? 470 ? 5pf dev i c e under te s t di gi t a l s c ope rise/fall time: 3.0 ns max. (measured between 0.6v and 2.4v ) pulse width: pw in = 1/(2*baud) period: per in = 1/baud note: the above conditions are for test only and do not in any way restrict the operation of the device. out tr i g in tr i g f i g u r e 2: t est s e t u p de v i ce unde r t est (d u t ) di gi t a l s c op e w avefo r m ge ne ra t o r out in com p ut e r sy st em pr in t e r figur e 3 : t i m i ng d i a g r a m t pl h t ph l per in pw in t ris e t fa l l 0. 6v 0. 6v 1. 5v 1. 5v 2. 4v 2. 4v 1. 5v 1. 5v v ih v il v oh v ol in p u t s ign a l ou tp u t s ign a l doc #06002 data delay devices, inc. 4 10/31/2007 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
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